This application is based upon and claims the benefit of priority of the prior Japanese Patent application No. 6-289883 filed on Nov. 24, 1994, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to an enhancement-type semiconductor device having an MIS (metal insulator semiconductor) structure and a fabrication process thereof, and relates, for example, to a ROM (read-only memory).
2. Related Arts
Heretofore, when structuring a mask ROM, an enhancement-type ROM transistor has been employed. Typically, a so-called ion-implantation type Rom is used wherein the threshold voltage is controlled by performing an ion implantation causing impurity ions to pass through a gate electrode to reach a channel region.
A fabrication process in a case for forming this ion-implantation type ROM using an N-channel transistor will be described with reference to FIGS. 15A through 15D.
In an N-channel transistor, a P-type silicon monocrystalline substrate 11 is oxidized in an oxidizing atmosphere of, for example, oxygen gas, a mixed gas of H2O and oxygen gas, or the like, to form a gate-oxide film 12, and thereabove is formed a gate electrode 13 of a polycrystalline silicon doped with, for example, a high concentration of phosphorus (FIG. 15A).
Next, a film 14 which is an amorphous oxide film or nitride film is formed to an appropriate thickness over the entire surface of the wafer so that ions implanted during ion implantation which will be described later do not cause channeling of the polycrystalline silicon gate electrode 13. Then, donor dopant (such as arsenic, phosphorus, or both) is implanted and a drain region 15a and source region 15b are formed (FIG. 15B).
Thereafter, in order to create an enhancement-type ROM, a photoresist 16 is formed, and acceptor dopant such as boron, BF2, or the like is implanted in the channel region using the patterned photoresist as a mask to form a high-concentration P-type region 17 of higher doping concentration than the substrate 11 over the entirety of the channel region (FIG. 15C).
Thereafter, a layer insulation film 18 composed of, for example, a BPSG film is formed over the entire surface, contact holes are formed in the layer insulation film 18 so as to reach the drain region 15a and source region 15b, respectively. Furthermore, a metal film of aluminum or the like is formed by a vapor deposition, sputtering, or chemical vapor growth process, and is patterned into a drain electrode 19a and source electrode 19b (FIG. 15D).
An enhancement-type ROM is formed according to the foregoing. Memory functions as this ROM are performed by establishing the doping concentration of the high-concentration P-type region 17. Additionally, in case this enhancement-type ROM is operated, the substrate 11 and source electrode 19b are set at, for example, 0 V, and the drain electrode 19a is set at 1 to 5 V. That is to say, the substrate 11 and source electrode 19b have the same; potential, and the drain electrode 19a is set at a higher potential.
However, in an enhancement-type ROM structure, as described above it is difficult to withstand voltage in a region of the channel region contiguous to the drain region 15a when compared when; ion implantation is not performed (i.e., when a high-concentration P-type region is not formed), this results in a problem in which leakage current from the drain region 15a to the substrate 11 or source region 15b is generated.
According to various investigations conducted by the inventors of the present application with respect to this problem, because a PN junction is defined between the e N-type drain region 15a of high concentration and the high-concentration P-type region 17 of the channel region and a high voltage of, for example, approximately 1 to 5 V with respect to the substrate 11 is applied to the drain region 15a, a Zener breakdown n or an avalanche breakdown occurs due to the foregoing PN junction, and thereby causing a large amount of leakage current becomes.
Moreover, the doping concentration of the high-concentration P-type region 17 formed on the entire surface of the channel region is on the order of 1018/cm3 when, for example, the doping concentration of the substrate 11 is approximately 1016xcx9c1017/cm3 and each doping concentration of the drain region 15a and source region 15b is approximately 1020/cm3.
Consequently, the higher the doping concentration of the high-concentration P-type region 17 of the channel region in order to increase threshold voltage in an enhancement-type ROM, the greater amount of leakage current is generated between the channel region and end portion of drain region 15a, and the more the withstand voltage declines. Power consumption also increases.
In light of the foregoing problems, it is an object of the present invention to suppress leakage current in a semiconductor device having an enhancement-type MOS structure.
To attain the object, the inventors devised forming the foregoing high-concentration P-type region 17 of the channel region not on the drain side, but from under the gate electrode to the source-region periphery in a semiconductor device having an enhancement-type MOS structure.
However, it was understood that even when a high-concentration P-type region is not formed on the drain region side, if an end portion of the high-concentration P-type region is proximate to an end portion of the drain region, leakage current does not decline sufficiently.
In regards to this structure when the operating voltage (for example 5 V) is actually applied to a transistor of enhancement-type MOS structure, a depletion layer expands from the PN junction between the drain region and channel region in accordance with the applied voltage, the depletion layer reaches the high-concentration P-type region and extends into the inside thereof, the electrical field intensity within the depletion layer increases sharply since it is difficult for the depletion layer to extend into the inside of a high-concentration region, the electrical field within the depletion layer becomes the critical field which causes avalanche breakdown or Zener breakdown even if the operating voltage is the maximum rated voltage, and thus leakage current is generated.
The present invention involves determining the position of the high-concentration P-type region so that, even if the depletion layer extending from the PN junction between the drain region and channel region reaches the high-concentration P-type region when operating voltage is applied, the electrical field within the depletion layer does not become the critical field which causes avalanche breakdown or Zener breakdown.
That is to say, a semiconductor device of MIS structure according to the present invention, which has a gate electrode formed on a semiconductor region with a gate insulation film interposed therebetween, source and drain regions making the semiconductor region therebetween a channel region, and a high-concentration region formed of the same conductivity type as the channel region and having a higher doping concentration than the channel region and disposed overlapping with the channel region, is characterized in that the high-concentration region is disposed remotely from at least the drain region, and that an end portion of the high-concentration region is established at a position such that an electrical field within a depletion layer which expands within the semiconductor region from a PN junction defined between the drain region and the semiconductor region toward the high-concentration region does not become the critical field causing avalanche breakdown or Zener breakdown when rated voltage of a time of actual usage is applied between the drain region and the semiconductor region.
Accordingly, when rated voltage is applied between the drain region and the semiconductor region, even if the depletion layer reaches and extends inside the high-concentration region, avalanche breakdown or Zener breakdown does not occur, and thereby suppressing increase in leakage current.
Additionally, it is sufficient if the position of the end portion of the high-concentration region, i.e., the distance between the end portion of the high-concentration region and the end portion of the drain region, is established so that the depletion layer extending from the PN junction between the drain region and the semiconductor region toward the high-concentration region does not reach the high-concentration region during actual usage when rated voltage is applied. The distance between the high-concentration region and the drain region is so adjusted as to preclude the depletion layer from reaching the high-concentration region at a voltage not more than the rated voltage, a marked increase in the electrical field intensity within the depletion layer more reliably is prohibited and thus increase in leakage current can be suppressed.
It is also acceptable for the high-concentration region to be disposed remotely from either the source region or the drain region. In this case, there is no occurrence of large leakage current in either case where the source region or the drain region is applied with an electrical potential which is high with respect to the semiconductor region.
The present invention can be employed as a MIS-type memory. In this case, suppressing leakage current during a stand-by mode prevents, wasteful power consumption.
Also, the present invention can be employed as a MIS-type memory which does not assume an xe2x80x9cONxe2x80x9d state during actual usage. In this case, because the memory is constantly in an xe2x80x9cOFFxe2x80x9d state, current does not flow. This suppresses, leakage current and further prevents wasteful power consumption.
On the other hand, a fabrication process for a semiconductor device according to the present invention is characterized by a step for forming a high-concentration region. As mentioned above, the high-concentration region is disposed overlapping a channel region which is a semiconductor region located under a gate electrode and between a source region and a drain region, and has the same conductivity type as the channel region. The high-concentration region forming steps of the present invention comprise: providing a mask for ion implantation so as to cover an entirety of the drain region and at least a drain side of the gate electrode; implanting first conductivity type impurity ions in a region not covered by the mask at an acceleration energy allowing the impurity ions to pass through the gate electrode; and forming the high-concentration region disposed remotely from at least the drain region such that an end portion thereof is established at a position where an electrical field within a depletion layer extending within the semiconductor region from a PN junction defined between the drain region and the semiconductor region toward the high-concentration region does not become the critical field causing avalanche breakdown or Zener breakdown when rated voltage during actual usage is applied between the drain region and the semiconductor region.
Consequently, a semiconductor device can be fabricated wherein the leakage current does not increase during a time of actual usage.
In particular, by selecting a position of the mask, it is possible for the high-concentration region to be located at a position where the depletion layer is precluded from reaching the end portion of the high-concentration region during the application of the rated voltage. In this case, since the depletion layer does not reach the high-concentration region, this suppresses a marked increase in the electrical field intensity within the depletion layer, and thus prevents an increase in leakage current.
Furthermore, establishment of the position of the end portion of the high-concentration region can be controlled by the position of the mask and the implantation angle of ion implantation. Consequently, degree of freedom of the establishment of the position of the end portion of the high-concentration region can be enlarged. That is to say, the position of the end portion of the high-concentration can freely be determined without altering the mask pattern.
It is acceptable to cause oblique ion implantation to form the high-concentration region so as to pass through only a side wall of the gate electrode. By doing so, it becomes possible to further suppress expansion of the high-concentration region to the drain region side. Consequently, it becomes still more difficult for the depletion layer extending toward the high-concentration region to reach the high-concentration region. Accordingly, gate-electrode width can be made smaller, and the semiconductor device can be made more compact.
Herein, performing the oblique ion implantation so that implanted ions pass through only the side wall of the gate electrode becomes attainable by forming the gate electrode of a multilayered structure composed of a main gate-electrode material and an ion-implantation inhibiting material for which passage of the impurity ions is more difficult than for the main gate-electrode material. By doing so, the position of the drain-side end portion of the high-concentration region can be defined by only impurity ions channeled from the side wall of the gate electrode, and it becomes possible to cause this end-portion position more proximately to the source-region side. That is to say, it becomes more difficult for the depletion layer to reach the high-concentration region at a time of rated-voltage application. This signifies that it becomes possible to cause gate-electrode width to be further narrowed, and further compactness of the semiconductor device becomes possible.
The main gate-electrode material may be a silicon-based material, and the ion-implantation inhibiting material may be composed of a metallic compound of metal and silicon. In this case, resistance as the gate electrode can be reduced, and increase in a resistance value of the gate electrode can be suppressed even when the gate electrode is made to be smaller.
When structuring such multilayered gate electrode, the main gate-electrode material and the ion-implantation inhibiting material may be laminated and simultaneously patterned. According to this method, the multilayered gate electrode can easily be formed.
The main gate-electrode pattern may be formed using main gate-electrode forming material. After forming the source region and drain region with this gate electrode as a mask, metal material is deposited on the gate-electrode pattern, source region and drain region and a heat treatment is performed. The metal compound can be formed between the metal material and the gate-electrode material and, a compound of semiconductor and metal material can be formed also between the source region and drain region. According, lowering of resistance of the gate electrode and of the source region and drain region can be simultaneously performed.